Lattice Semiconductor
10Gb Ethernet XGXS IP Core User’s Guide
Figure 9. XGXS Loopback Capabilities
ORT82G5
ORT82G5
xgmii_tx_dat_sel
xgxs_lb_signal
FPGA
Array
Embedded
Core
XGMII TX
data & control
XGMII
TX
DDR
Input
Packet
Generator
SEL
XGMII
loopback
SEL
XGXS
loopback
XGXS
TX
Encoder
XAUI
loopback
Packet
Checker
XGMII RX
data & control
XGMII
RX
DDR
Output
SEL
XGXS
RX
Encoder
xgmii_lb_signal
Inject Error Capability
An active low input ( inj_err_n ) is provided that supports the ability to inject errors in the packet generator trans-
mit path. One errored packet is generated each time inj_err_n is pulsed low. The error injected may occur any-
where within the packet, but will only occur within the data cycle phase, and not while special characters are being
sent. If inj_err_n is active after the end of a packet, the XGXS waits until after the next start of packet to inject
the error.
Automatic Con ? guration Capability
The XGXS IP supports the ability to automatically con ? gure the ORT82G5 embedded core upon power up or hard-
ware/software reset. This capability automatically sets all appropriate embedded registers to enable QUAD B
Channel alignment in XAUI mode. Automatic con ? guration of the embedded core is enabled or disabled using the
external pin “pwrup_init_en” (active high - automatic con ? guration enabled).
Automatic con ? guration performs the sequence of operations speci ? ed in the following list. Equivalent con ? guration
may be performed via the MDIO or SYSBUS interface.
In the following list:
? mmb = write memory byte. The command is followed by a hex address value and a hex data value.
? dmb = read memory byte. A hex address value and the number of consecutive addresses to read follow the com-
mand.
Con ? guration Steps
1. mmb 30105 64 ; do a software reset
2. dmb 30105 1 ; wait for a while
3. dmb 30105 1 ; wait for a while
4. mmb 30105 44 ; remove software reset
5. mmb 30A00 00 ; set RX and TX clock selects to BA
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